Architecting Mobile Process-In-Memory Accelerators for Convolutional Neural Networks
報告題目：Architecting Mobile Process-In-Memory Accelerators for Convolutional Neural Networks
時 間：2018年8月29日（周三）上午10:00
地 點：421會議室
報告人：Prof. Lei Jiang, Indiana University Bloomington
摘要：It is extremely challenging to deploy computing intensive convolutional neural networks (CNNs) with rich parameters in mobile devices because of their limited computing resources and low power budgets. Delivering highly accurate CNN tests for all simultaneous applications will exhaust available hardware and power resources of mobile devices. Therefore, a mobile CNN accelerator must allow a graceful trade-off between test accuracy, latency and energy consumption. In this talk, I will discuss about architecting mobile process-in-memory (PIM) accelerators for convolutional neural networks by two types of memory technologies: DRAM and 3D XPoint ReRAM. Two PIM accelerators aim to provide various test accuracies to applications with different priorities and dynamically exploit the trade-off between test accuracy and latency.
報告人簡介： Prof. Jiang is an assistant professor in the department of intelligent systems engineering at Indiana University Bloomington. He obtained is Ph.D. from University of Pittsburgh, M.S. and B.S. from Shanghai Jiao Tong University. His research interests are accelerator designs and emerging nonvolatile memory technologies. Prof. Jiang published a series of paper in the top conferences and journals of computer architecture, such as ASPLOS, ISCA, MICRO, HPCA, DSN, ICCAD, DAC, TACO and TCAD. He also served as the technical program committee member of DAC, ICCD, ASP-DAC and NVMSA.